Buffer circuit for outputting signals of different polarities

Details Buffer circuit for outputting signals of different polarities Buffer circuit for outputting signals of different polarities

1987-02-17

1988-11-08

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307570, 307443, 307269, H03K 602, H03K 3353, H03K 1710, H03K 17687

Patent

active

047836040

ABSTRACT:
A buffer circuit comprises first to third CMOS inverters whose input terminals are mutually connected, first and second npn transistors whose bases are commonly connected to an output terminal of the first CMOS inverter and whose emitters are respectively connected to output terminals of the second and third CMOS inverters, fourth and fifth CMOS inverters for inverting the output signals of the first and third CMOS inverters, a third npn transistor whose base and emitter are respectively connected to output terminals of the fourth and fifth CMOS inverters, fourth and fifth npn transistors whose conduction states are controlled by the output signals of the first and fourth CMOS inverters, first and second n-channel MOS transistors which are serially connected to the fourth and fifth npn transistors, respectively, and whose gates are respectively connected to the third and fifth CMOS inverters, and third and fourth n-channel MOS transistors which are respectively connected between the gates of the first and second n-channel MOS transistors and a reference voltage terminal and whose gates are respectively connected to the fourth and first CMOS inverters.

REFERENCES:
patent: 4291247 (1981-09-01), Cooper, Jr. et al.
patent: 4479216 (1984-10-01), Krambeck et al.
patent: 4495426 (1985-01-01), Leach
patent: 4618786 (1986-10-01), Johnson
patent: 4625126 (1986-11-01), Tinker et al.
patent: 4649295 (1987-03-01), McLaughlin et al.
patent: 4678940 (1987-07-01), Vasseghi et al.
patent: 4694203 (1987-09-01), Uragami et al.
patent: 4701642 (1987-10-01), Pricer

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