Switched-capacitor multiplier circuit

Details Switched-capacitor multiplier circuit Switched-capacitor multiplier circuit

1986-06-26

1987-12-29

LaRoche, Eugene R.

Demodulators

Amplitude modulation demodulator

Having specific distortion, noise or other interference...

329110, 331 25, 328151, 328160, 455323, H03D 318, H03K 500, H03K 1700

Patent

active

047163755

ABSTRACT:
A switched-capacitor multiplier circuit for multiplying an information signal x(t) by a bipolar carrier signal d(t) consisting of a distributed multiplier circuit with which the bipolar carrier signal is normally associated. To reduce offset voltages in the output signal caused by the operational amplifiers used and caused as a result of clock feed-through, it is not the bipolar carrier signal itself, but a full-wave rectified version thereof that is associated with the distributed multiplier circuit. The output signal of the multiplier circuit is applied to an auxiliary multiplier circuit multiplying it by +1 or -1 dependent on the instantaneous polarity of the bipolar carrier signal d(t). The offset voltage is thereby transposed to a frequency which is at least equal to the fundamental frequency of the carrier signal so that, if desired, it can be suppressed with the aid of a suitably chosen low-pass filter without the desired signal being affected thereby.

REFERENCES:
patent: 4439693 (1984-03-01), Lucas et al.
patent: 4517655 (1985-05-01), Claasen et al.
patent: 4531106 (1985-07-01), Ganesan
patent: 4569072 (1986-02-01), Claasen et al.
patent: 4616185 (1986-10-01), van Roermund
patent: 4616192 (1986-10-01), van Roermund

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