Fabrication of double diffused metal oxide semiconductor transis

Details Fabrication of double diffused metal oxide semiconductor transis Fabrication of double diffused metal oxide semiconductor transis

1986-06-05

1987-12-29

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 29, 437 69, 437 41, H01L 21265, H01L 21316

Patent

active

047161264

ABSTRACT:
In the fabrication process of a DMOS transistor, a window is formed between polysilicon gate regions. Nitrogen is then implanted in the window. A self-aligning oxide is deposited to cover the exposed side walls of the polysilicon gate regions. P-type impurities are implanted at the exposed surface of the window between the side walls. Using silicon nitride masking, an oxide plug is then grown in the window. N-type impurities are implanted in the window region to form a junction adjacent to the polysilicon gate regions. Metal contacts and a passivation layer are subsequently deposited by masking, and contact windows are formed to complete the transistor structure.

REFERENCES:
patent: 4417385 (1983-11-01), Temple
patent: 4430792 (1984-02-01), Temple
patent: 4443931 (1984-04-01), Baliga et al.
patent: 4466176 (1984-08-01), Temple
patent: 4567641 (1986-02-01), Baliga et al.
patent: 4644637 (1987-02-01), Temple

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