Fishing – trapping – and vermin destroying
Patent
1989-12-18
1990-08-14
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 47, 437 52, 437200, 437228, 437233, 437235, 437918, 357 51, H01L 2140, H01L 2190
Patent
active
049487477
ABSTRACT:
A process for fabricating an integrated circuit resistor is disclosed. In accordance with one embodiment of that invention a first thin layer of silicon is deposited to overlay a semiconductor substrate. That thin layer of silicon is doped to a predetermined level to establish the proper conductivity desired for the integrated circuit resistor being formed. The first layer of silicon is patterned to form a first resistor layer and a second interconnect area with the two areas being in contact. A layer of insulating material is formed over the resistor area to mask the resistor area from subsequent processing steps. A second layer of silicon is deposited by a process of selective deposition onto the exposed interconnect areas of the first thin layer of silicon and that selectively deposited silicon is heavily doped with conductivity determining impurity material to reduce the resistivity thereof.
REFERENCES:
patent: 4290185 (1981-02-01), McKenny et al.
patent: 4445266 (1984-05-01), Mai et al.
patent: 4451328 (1984-05-01), Dubois
patent: 4859279 (1989-08-01), Choi
Fisher John A.
Hearn Brian E.
Motorola Inc.
Thomas T.
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