Process for elevated source/drain field effect structure

Details Process for elevated source/drain field effect structure Process for elevated source/drain field effect structure

1989-05-22

1990-08-14

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 44, 437 46, 437 56, 437 57, 437 89, 437 99, 437191, 437233, H01L 21336

Patent

active

049487450

ABSTRACT:
A process for the fabrication of elevated source/drain IGFET devices is disclosed. In accordance with one embodiment of the process, a silicon substrate is provided which is divided into active and field regions by a field oxide. A gate oxide is formed over the active region and a thin layer of polycrystalline silicon and a thick layer of silicon nitride are deposited on the gate oxide. The polycrystalline silicon and the silicon nitride are etched to form a stacked structure, with the spacers having substantially the same height as the stacked structure, in the pattern of the gate electrode. Sidewall spacers are formed on the edges of the stacked structure and the silicon nitride is removed. Polycrystalline silicon is then deposited onto the polycrystalline silicon and the exposed portions of the source and drain regions to complete the gate electrode and to form the source and drain electrodes. The selectively deposited polycrystalline silicon extends upwardly from the source and drain regions onto the field oxide. The sidewall spacers provide physical and electrical isolation between the gate electrode and the adjacent source and drain electrodes.

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S. S. Wong et al., "Elevated Source/Drain Mosfet", IEDM 1984, pp. 635-637.

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