Method and apparatus for high speed integrated circuit testing

Details Method and apparatus for high speed integrated circuit testing Method and apparatus for high speed integrated circuit testing

1989-03-23

1990-11-20

Smith, Jerry

Excavating

371 251, 371 27, G06F 1100

Patent

active

049724134

ABSTRACT:
An apparatus for use in high speed digital testing of high pin count logic circuits is provided wherein a plurality of terminal electronics units are connected in series to each other and to one channel of a multi-channel tester. Each pin electronics unit stores a test vector from the test channel in a first mode, and applies the test vector to the circuit under test at high speed in a second mode. Each pin electronics unit can also store response data from the circuit under test.

REFERENCES:
patent: 4287594 (1981-09-01), Shirasaka
patent: 4348759 (1982-09-01), Schnurmann
patent: 4566104 (1986-01-01), Bradshaw
patent: 4571724 (1986-02-01), Belmondo

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