High speed data logical comparison device

Details High speed data logical comparison device High speed data logical comparison device

1979-08-24

1981-05-26

Malzahn, David H.

Communications: electrical

Digital comparator systems

G06F 704

Patent

active

042701163

ABSTRACT:
Reference logical data is spatially divided by a data dividing circuit for each time slot, and the divided data are converted into data, each having a continuous effective period. The divided and converted reference data and input logical data are compared by comparators to detect whether or not they are coincident with each other. A clock signal for determining the timing of comparison is also divided by a clock signal dividing circuit into n clock signals which are displaced one time slot apart in phase and occurring with a period of n time slots. By these divided clock signals those of the outputs from the comparators corresponding thereto are taken out from a comparison output circuit.

REFERENCES:
patent: 3660823 (1972-05-01), Recks
patent: 3694642 (1972-09-01), Grannis
patent: 3784980 (1974-01-01), Geesen

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