Computer graphics processing and selective visual display system – Display driving control circuitry – Controlling the condition of display elements
Patent
1997-04-16
1998-08-25
Shah, Alpesh M.
Computer graphics processing and selective visual display system
Display driving control circuitry
Controlling the condition of display elements
345516, G06F 300
Patent
active
057992029
ABSTRACT:
A video terminal architecture and an associated management circuit for managing the display of the video terminal are dislcosed. The terminal architecture includes a microprocessor (81) connected to the management circuit (85) via a first data bus (8549) and a first address bus (8558). The management circuit (85) manages the video display and accesses to a video memory VRAM (83). The VRAM includes the system memory and the display memory. The management circuit (85) is memory and the display memory. The management circuit (85) is also connected to a read-write character generator memory (82) via a second address data bus (8529), a second data bus (8529), and by five output lines to the video monitor.
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IBM Technical Disclosure Bulletin, vol. 26, No. 4, Sep. 1983, Direct Extraction Of Data From The Refresh Buffer Of A Display G. J. Barnett, et al.; pp. 2156-2158; p. 2157, line 10-line 29; Fig. 1.
Kondracki Edward J.
Shah Alpesh M.
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