Level shift circuit for achieving a high-speed processing and an

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307446, 307264, 330257, H03K 19092, H03K 19094, H03K 1901, H03K 1704

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active

050755790

ABSTRACT:
A level shift circuit of the present invention includes an input differential pair of transistors, as an input circuit section, which are switchingly operated in accordance with the level of an input signal supplied from a preceding circuit. An output circuit section is composed of first and second emitter follower transistors. A third transistor has its current path connected at one end to an emitter of the first emitter follower transistor and makes an output level of the first emitter follower transistor at a predetermined level. A fourth transistor has its current path connected at one end to the other end of the reference potential and its gate electrode connected to an output terminal of the second emitter follower transistor and is driven by an output voltage of the second emitter follower transistor to allow an output level of the first emitter follower transistor to be shifted to a low level. An inverter is connected to the output of the first and second emitter follower transistors and comprised of a P- and N-channel transistors commonly connected at their adjacent current paths to each other. The inverter is operated in accordance with an output level of the first emitter follower transistor to allow an output level of the second emitter follower tansistor to be output from that common connection point.

REFERENCES:
patent: 4379267 (1983-04-01), Young
patent: 4563601 (1986-01-01), Asano et al.
patent: 4697109 (1987-09-01), Honma et al.
patent: 4797583 (1989-01-01), Ueno et al.
IEEE Journal of Solid-State Circuits, vol. 23, No. 5, dated Oct. 1988, pp. 1036-1037 by Yang et al.

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