Failure recovery informing arrangement with simplified hardware

Details Failure recovery informing arrangement with simplified hardware Failure recovery informing arrangement with simplified hardware

1988-07-20

1991-03-12

Atkinson, Charles E.

Excavating

364200, 371 14, G06F 1100

Patent

active

049998382

ABSTRACT:
When a peripheral control processor is put, in a data processing system, into a down state from a normal state of operation upon occurrence of a failure, a failure recovery informing arrangement comprises a failure occurrence signal producing circuit for delivering a failure occurrence signal to a diagnostic bus. Detecting the failure occurrence signal, a detecting circuit delivers a detection signal to a system bus. Responsive to the detection signal, a recovery command signal producing circuit delivers a recovery command signal back to the system bus rather than, through a specific hardware line, directly to the peripheral control processor. Instead of the specific hardware line, a processing circuit is used in processing the recovery command signal into a peripheral initializing signal and a recovery informing signal to supply them to the peripheral control processor through the diagnostic bus. The initializing signal is for turning the down state to the normal state. The informing signal informs that the down state is turned back to the normal state. Upon occurrence of a system failure, a start signal is manually or otherwise supplied to the processing circuit and processed into a system initializing signal and a start information signal which are delivered to the peripheral control processor like the peripheral initializing and the recovery informing signals. Preferably, a diagnostic test program is preliminarily memorized in the peripheral control processor and is used in response to the initializing and the informing signals in turning the down state to the normal state.

REFERENCES:
patent: 4048481 (1977-09-01), Bailey, Jr. et al.
patent: 4521847 (1985-06-01), Ziehm et al.

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