Full adder with short signal propagation path

Details Full adder with short signal propagation path Full adder with short signal propagation path

1989-03-07

1991-03-12

Shaw, Dale M.

Boots, shoes, and leggings

G06F 750

Patent

active

049998048

ABSTRACT:
A full adder has a carry producing circuit responsive to at least two input bits and a low order carry bit and producing a carry bit, and a sum producing circuit responsive to the two input bits, the low order carry bit and the carry bit and producing a sum bit, wherein the sum producing circuit is provided with a first sum producing portion activated in the co-presence of the two input bits of logic "1" level or logic "0" level and the low order carry bit of logic "1" level or logic "0" level to produce the sum bit, and a second sum producing portion activated in the co-presence of at least one of the input bits and the low order carry bit different in logic level from the other bits to produce the sum bit opposite in logic level to the carry bit, so that signal propagation path is reduced in length, thereby achieving a high speed operation.

REFERENCES:
patent: 3878986 (1975-04-01), Hirasawa
patent: 4583192 (1986-04-01), Cieslak
patent: 4601007 (1986-07-01), Uya et al.
patent: 4651296 (1987-03-01), Koike

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