Floating point arithmetic system and method

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G06F 738

Patent

active

049998030

ABSTRACT:
System and method for reducing the processing time or latency of floating point arithmetic operations by eliminating the need to complement a negative result produced by a subtraction operation. Each of two numbers is subtracted from the other in simultaneous parallel subtraction operations to produce one answer which is positive and one answer which is negative. The answer which is positive is selected as the result of the operation.

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