Split replacement cycles for sectored cache lines in a 64-bit mi

Details Split replacement cycles for sectored cache lines in a 64-bit mi Split replacement cycles for sectored cache lines in a 64-bit mi

1995-04-19

1997-03-11

Kim, Matthew M.

395403, 395470, 395471, 395473, 395496, 395855, 395307, G06F 1208

Patent

active

056110715

ABSTRACT:
A procedure for implementing cache line replacement cycle as split replacement cycles is used in a 64/32 computer system including a 64-bit x86 microprocessor interfaced to a 32-bit x86 bus architecture which does not support pipelined bus cycles. The microprocessor includes an internal L1 cache with two sectors S0 and S1 per cache line such that a cache line replacement request involving both sectors is performed as a split replacement cycle with a separate burst write cycle for each sector. The microprocessor's bus interface unit (BIU) includes (a) a BCC register which is used to stage the first sector (S0) of a split replacement cycle as the current bus cycle, and (b) a BNC register, which is used in a pipelined 64-bit bus architecture to stage pipelined bus cycles, but is used in the exemplary 64/32 system to stage the second sector (S1) of the split replacement cycle. For normal split replacement cycles, the BIU (a) runs the first burst write cycle to transfer S0 from BCC, (b) transfers the S1 to BCC, and (c) runs the second burst write cycle. If the first burst write cycle is interrupted by BOFF#, and if the cache inquiry hits on S1 in BNC, the BIU implements a combined replacement/snoop write-back cycle with sector reordering by (a) running the snoop write-back cycle to transfer S1 from BNC, and (b) rerunning the first bus cycle to transfer S0 from BCC. Thus, the normal replacement cycle order of S0/S1 is reordered to S1/S0 due to the intervening BOFF# write-back of S1.

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