Method and processor for reliably processing interrupt demands i

Details Method and processor for reliably processing interrupt demands i Method and processor for reliably processing interrupt demands i

1993-11-24

1997-03-11

Teska, Kevin J.

Boots, shoes, and leggings

3642318, 3642474, 3642477, 3649613, 3642632, 364DIG1, G06F 900

Patent

active

056110618

ABSTRACT:
A processing method by a processor operating under a pipeline control mode, in which first instruction information data are fetched in a first operating cycle of a series of operating cycles and processing in accordance with the first instruction information data is executed in the following second operating cycle, at the same time that second instruction information data is fetched. When an interrupt demand is made in a given operating cycle, address data of Instruction information data fetched during the operating cycle and address data of instruction information data fetched during an operating cycle following the operating cycle are saved. Instruction information data specified by the two address data are fetched and executed on termination of an interrupt processing performed in response to the interrupt demand.

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Limbach & Limbach LLP

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