Synchronization slicer

Details Synchronization slicer Synchronization slicer

1985-10-17

1987-06-30

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307354, 307358, 307362, 328147, H03K 5153

Patent

active

046773886

ABSTRACT:
There is disclosed herein an apparatus and method for accurately ascertaining the time of occurrence of passage of the leading and trailing edges of an input pulse through the 50% amplitude level. The apparatus implements the transfer function 1 - cos(wt) where t is equal to the round trip delay through a delay line, and w is the angular velocity of each fourier component of the input signal. In one embodiment, a summing resistor and a delay line having a characteristic impedance equal to that of the resistor are used. The output of the delay line is coupled to one input of a comparator, and the other input is coupled to the junction between the summing resistor and the delay line. Another embodiment uses two matched delay lines, two factoring circuits, a summing circuit and a comparator to implement the same transfer function.

REFERENCES:
patent: 3532905 (1970-10-01), Zijta et al.
patent: 3676783 (1972-07-01), Kinbara et al.
patent: 3763436 (1973-10-01), Haw
patent: 3942038 (1976-03-01), Hutch
patent: 4507795 (1985-03-01), Wagner

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