Semiconductor memory device having a hierarchical bit line struc

Static information storage and retrieval – Addressing – Plural blocks or banks

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36518901, 365202, 365203, 365207, 36523005, G11C 800

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active

056108710

ABSTRACT:
Bit lines includes sub-bit lines arranged corresponding to respective memory cell column groups, and also includes main bit lines MBLa and MBLb. When selecting a word line, a separation transistor is turned off, so that the main bit line is divided into two divided main bit lines, and a memory group including the selected word line and a memory cell block which is disposed at a symmetrical position with respect to the separation transistor are selected. After the separation transistor is turned off, sense amplifiers perform sensing operation. Influence against the sensing operation, which may be caused by noises due to a bit line capacitance, is prevented, and the hierarchical bit lines are accurately equalized and precharged.

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patent: 5367488 (1994-11-01), An
"Experimental 4-Mbit Peripheral CMOS Dynamic RAM Using a Trench-Type Transistor Cell", Shichijo et al., Nikkei Electronics, Jul. 14, 1986, pp. 189-208.
"Bidirectional Matched Global IT Line Scheme for High Density DRAMs", J. H. Ahn et al, 1993 Symposium on VLSI CIrcuit, Digest of Technical Papers, May 1993, pp. 91-92.

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