Circuit and method for controlling the impedance of a serial acc

Details Circuit and method for controlling the impedance of a serial acc Circuit and method for controlling the impedance of a serial acc

1996-03-28

1997-03-11

Nelms, David C.

Static information storage and retrieval

Powering

365221, 365149, G11C 1300

Patent

active

056108702

ABSTRACT:
A circuit for controlling a serial access memory is disclosed. A memory cell array is accessed through a pair of bit lines. One or more registers are provided for receiving and storing data through the bit lines. Sequential transmission switches connect the registers to associated data buses, and are sequentially activated in accordance with selection signals of an address decoder. A circuit in accordance with the invention further includes a multi-stage impedance controlling means for controlling the impedance of a power line for the registers through three or more stages during a data transmission. The impedance controlling means includes first and second MOS transistors connected in parallel between a power source and the registers. The first MOS transistor has a gate connected to a control signal for forming a high impedance at some point in time during a data transmission, and the second MOS transistor has a gate connected to a fixed voltage. The first and second MOS transistors are PMOS transistors, and the gate of the second MOS transistor is connected to a ground potential.

REFERENCES:
patent: 4281401 (1981-07-01), Redwine et al.
patent: 4322635 (1982-03-01), Redwine
patent: 4667313 (1987-05-01), Pinkham et al.
patent: 4864544 (1989-09-01), Spark et al.
patent: 4947373 (1990-08-01), Yamaguchi et al.
patent: 5327386 (1994-07-01), Fudeyasu

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