Signal processing device

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348476, H04N 715

Patent

active

056108400

ABSTRACT:
A signal processing device has a memory in which a digital image signal is stored, and a data bus including a plurality of signal liens is connected to the memory. A pull-up resistance is connected to a predetermined signal line, and the other signal lines are connected to the ground through pull-down resistances. A blanking signal BLK3 at a low level is inputted into an output enable terminal of the memory, so that the output terminal of the memory becomes high-impedance, and thus a digital signal corresponding to a pedestal level is outputted through the data bus and a blanking period is formed. The pedestal level is determined by the position of the pull-up resistance.

REFERENCES:
patent: 3705260 (1972-12-01), Okada
patent: 3927255 (1975-12-01), Yorkanis
patent: 4298885 (1981-11-01), Okada
patent: 4729026 (1988-03-01), Suzuki et al.
patent: 5153740 (1992-10-01), Sato
patent: 5334998 (1994-08-01), Priem et al.

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