Error correction control system for control memory

Details Error correction control system for control memory Error correction control system for control memory

1988-03-04

1990-09-04

Atkinson, Charles E.

Excavating

364200, G06F 1100

Patent

active

049550233

ABSTRACT:
An error correction control system for a control memory generates, when an error is detected in a microinstruction read out from a control memory to a microinstruction register, a first inhibit signal for inhibiting an updating the microinstruction register, and generates a second inhibit signal at the timing one clock period after the first inhibit signal is generated. After an error correction sequence is completed, the second inhibit signal is disabled at a timing one clock period after the first inhibit signal is disabled.

REFERENCES:
patent: 4641305 (1987-02-01), Joyce et al.
patent: 4701915 (1987-10-01), Kitamura et al.

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