Swap control apparatus for hierarchical memory system

Details Swap control apparatus for hierarchical memory system Swap control apparatus for hierarchical memory system

1985-11-06

1988-03-22

Williams, Jr., Archie E.

Boots, shoes, and leggings

G06F 1318

Patent

active

047333677

ABSTRACT:
In a multiple-block-per-entry buffer memory (BS) of the swap or store-in type, a swap-out buffer (SOB) having a capacity for at least a block is provided. On the occasion of replacing, a memory access sequence control responds to change bits and validity bits associated with an entry to be replaced as well as the block address designated for memory access so as to execute the data transfer from a main memory (MS) to BS in preference to the sweeping-out of data from BS to SOB so long as the block to be replaced need not be stored in MS. If the block to be replaced needs to be stored, the sweeping-out into SOB is executed with the utmost priority, and the data transfer from MS is then executed in preference to the sweeping-out of any other blocks to be stored into MS.

REFERENCES:
patent: 4323968 (1982-04-01), Capozzi
patent: 4395763 (1983-07-01), Takahashi
patent: 4550367 (1985-10-01), Hattori et al.

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