Software debugging system for writing a logical address conversi

Details Software debugging system for writing a logical address conversi Software debugging system for writing a logical address conversi

1988-11-17

1990-09-04

Williams, Jr., Archie E.

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364231, 36423131, 3642323, 364240, 3642399, 3642447, 3642558, 3642566, 3642596, 3642604, 3642804, G06F 9455, G06F 1210, G06F 1128

Patent

active

049549421

ABSTRACT:
The microprocessor has an address converting buffer to convert logical addresses into physical addresses and a signal generator representing the timing for the microprocessor to retrieve conversion information from an external memory and write it into the address converting buffer. With this configuration, it is possible to determine the logical address from the physical address that was output to an external circuit, without the microprocessor outputting the logical address directly to the external circuit.

REFERENCES:
patent: 4218743 (1980-08-01), Hoffman et al.
patent: 4574351 (1986-03-01), Dang et al.
patent: 4636940 (1987-01-01), Goodwin, Jr.
"Virtual Address Trace Mechanism", Greer et al., IBM Technical Disclosure Bulletin, vol. 26, No. 2, Jul. 1983.
"Nikkei Electronics", Nikkei McGraw-Hill, No. 414, Feb. 9, 1987, pp. 101-102.

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