Improved purge arrangement for an address translation control sy

Details Improved purge arrangement for an address translation control sy Improved purge arrangement for an address translation control sy

1984-12-17

1988-03-22

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 1208

Patent

active

047333502

ABSTRACT:
An address translation control system comprising an address translation buffer having a plurality of entries each including at least a valid flag, a logical address field, and a physical address field, a memory array having copies of at least the valid flag and the physical address field, and a purge register for storing information showing a portion of the contents of the address translation buffer to partially purge the address translation buffer. When coincidence between the physical address of the address translation buffer and the contents of the purge register does not occur, ordinary access processing is carried out, and when entry of the memory array is accessed in turn and coincidence between the physical address in the memory array and the contents of the purge register occurs, purge is performed by clearing the valid flags of the corresponding entries of the address translation buffer and the memory array. Thus, purge processing can be carried out separately from the ordinary access processing, and the application efficiency for the address translation buffer increases. Particularly, the performance efficiency for the application of this invention to a pipeline system or a virtual machine can be increased.

REFERENCES:
patent: 4053948 (1977-11-01), Hogan et al.
patent: 4068303 (1978-01-01), Morita
patent: 4163288 (1970-07-01), Vinot
patent: 4373179 (1983-02-01), Katsumata
patent: 4376927 (1983-03-01), Anderson et al.
patent: 4481573 (1984-11-01), Fukunaga et al.
IBM Technical Disclosure Bulletin, "System for Purging TLB", by Coscarella and Sellers, vol. 24, No. 2, Jul. 1981.
IBM Technical Disclosure Bulletin, "Fast Purging for an Array Table", by Lin, vol. 23, No. 3, Aug. 1980.

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