Gate-array chip

Details Gate-array chip Gate-array chip

1986-02-10

1988-03-22

James, Andrew J.

357 45, 357 68, H01L 2702

Patent

active

047332883

ABSTRACT:
A gate-array chip includes a plurality of basic-cell arrays arranged in parallel on a semiconductor bulk and a plurality of impurity regions formed on the semiconductor bulk and in regions between the basic-cell arrays. The impurity regions and part of the basic-cell arrays are adapted to form input/output circuits whereby the gate-array chip is divided into several chips each having a desired size and a desired number of gates.

REFERENCES:
patent: 3839781 (1974-10-01), Russell
patent: 3849872 (1974-11-01), Hubacher
IBM Technical Disclosure Bulletin, vol. 14, #9, Feb. 72, "Formation of Kerf . . . on Semiconductor Wafers", by Mandia et al.
IBM Tech. Disc. Bulletin, vol. 14, #12, May 72, by Tsui: "Masterslice Concept for Multiple Chip Sizes".
IBM Tech. Disc. Bulletin, vol. 22, #4, Sep. 79, by Ballista et al., "Logic Masterslice Design".
Electronic Engineering, vol. 54, No. 663, Mar. 1982, "Designing with ULA's; Part 1: Technology and Circuits Elements", pp. 53-57.
IEEE Journal of Solid-State Circuits, vol. SC-16, No. 5, Oct. 1981, "CMOS/SOS Automated Universal Array", by Borgini et al., pp. 563-570.

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