Semiconductor memory integrated circuit and process of fabricati

Details Semiconductor memory integrated circuit and process of fabricati Semiconductor memory integrated circuit and process of fabricati

1988-12-05

1990-02-06

James, Andrew J.

357 51, 357 49, 357 55, H01C 2172

Patent

active

048992038

ABSTRACT:
In a semiconductor memory integrated circuit device having a stacked capacitor cell, a first plate electrode and a first dielectric film are formed underneath a charge storage electrode a charge storage electrode, and a second dielectric film and a second plate electrode are formed over the charge storage electrode. The charge storage electrode has contact with the diffusion region through a contact hole penetrating the first dielectric material. The first and second plate electrodes are connected via a contact hole penetrating the first and second electric films outside the cell area. Because both the upper surface and the lower surface of the charge storage electrode are utilized for formation of the capacitor the size of the capacitor can be halved to produce the same capacitance.

REFERENCES:
patent: 4700457 (1987-10-01), Matsukawa
63.7 mm.sup.2 4MDRAM with proportion-reduced stacked-cells; Nakano et al.; pp. 117 to 130 of Annex No. 1 of Nikkei Micro Device "Jitsuyoka ni Mukete Shidousuru 4MDRAM no Zenbou (The Entire Picture of 4 Mbit DRAM Starting for Commercialization)" pp. 117 to 130, and pp. 165 to 174.
Basic Functions Have Been Confirmed with 110.9 mm.sup.2 Full-Scale TEG Employing Stacked-Capacitor Cells; Shimnizu, et al.; pp. 165 to 174 of Annex No. 1 of Nikkei Micro Device "Jitsuyoka ni Mukete Shidousuru 4MDRAM no Zenbou (The Entire Picture of 4 Mbit DRAM Starting for Commercialization)".

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