Shared memory multiprocessor system and method of operation ther

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395200, 364DIG1, 364245, 3642431, 3642434, 36424342, G06F 100

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052972658

ABSTRACT:
A digital data processing apparatus has plural processing cells, each with a memory element that stores data page made up of plural subpages. At least one of the cells includes a CPU that can request access to a data subpage. A memory manager responds to selected data access requests by (i) allocating, within the memory local to the requesting CPU, exclusive physical storage space for a data page associated with the requested subpage, and (ii) storing the requested subpage in that allocated space. The apparatus recombines data pages and deallocates them on the basis of usage and access state. The apparatus also accesses data asynchronously with respect to execution of instructions by the CPU.

REFERENCES:
patent: Re28811 (1976-05-01), Pierce
patent: 3713096 (1973-01-01), Comfort et al.
patent: 3723976 (1973-03-01), Alvarez et al.
patent: 3731002 (1973-05-01), Pierce
patent: 3735362 (1973-05-01), Ashany et al.
patent: 3748647 (1973-07-01), Ashany et al.
patent: 3885742 (1989-12-01), Yano
patent: 4011545 (1977-03-01), Nadir
patent: 4031512 (1977-06-01), Faber
patent: 4077059 (1978-02-01), Cordi et al.
patent: 4141067 (1979-02-01), McLagan
patent: 4240143 (1980-12-01), Besemer et al.
patent: 4245306 (1981-01-01), Besemer et al.
patent: 4293910 (1981-10-01), Flusche et al.
patent: 4322795 (1982-03-01), Lange et al.
patent: 4334305 (1982-06-01), Girardi
patent: 4358823 (1982-11-01), McDonald
patent: 4394731 (1983-06-01), Flusche et al.
patent: 4410946 (1983-10-01), Spencer
patent: 4432057 (1984-02-01), Daniell et al.
patent: 4468733 (1984-08-01), Oka et al.
patent: 4484262 (1984-11-01), Sullivan et al.
patent: 4503497 (1985-03-01), Krygowski et al.
patent: 4510492 (1985-04-01), Mori et al.
patent: 4598400 (1986-07-01), Hillis
patent: 4604694 (1986-08-01), Hough
patent: 4622631 (1986-11-01), Frank et al.
patent: 4625081 (1986-11-01), Lotito et al.
patent: 4646271 (1987-02-01), Uchiyama et al.
patent: 4700347 (1987-10-01), Rettberg et al.
patent: 4701756 (1987-10-01), Burr
patent: 4706080 (1987-11-01), Sincoskie
patent: 4714990 (1987-12-01), Desyllas et al.
patent: 4734907 (1988-03-01), Turner
patent: 4754394 (1988-06-01), Brantley, Jr. et al.
patent: 4758946 (1988-07-01), Shar et al.
patent: 4792895 (1988-12-01), Tallman
patent: 4797880 (1989-01-01), Bussey, Jr. et al.
patent: 4811009 (1989-03-01), Orimo et al.
patent: 4811203 (1989-03-01), Hamstra
patent: 4814970 (1989-03-01), Barbagelata et al.
patent: 4829227 (1989-05-01), Turner
patent: 4845702 (1989-07-01), Melindo
patent: 4864495 (1989-09-01), Inaba
patent: 4888726 (1989-12-01), Struger et al.
patent: 4951193 (1990-08-01), Muramatsu et al.
patent: 4972338 (1990-12-01), Crawford
patent: 4980816 (1990-12-01), Fukuzawa et al.
patent: 4984235 (1991-01-01), Hillis et al.
patent: 5006978 (1991-04-01), Neches
patent: 5025366 (1991-06-01), Baror
patent: 5060186 (1991-10-01), Barbagelata et al.
patent: 5101402 (1992-03-01), Chiu et al.
Lovett et al., Proceedings '88 Int'l. Conf. on Parrell Proc., vol. 1, Penn State Univ. Press (Conf. Aug. 15-19, 1988) pp. 303 et seq.
Kai Li et al., Proceedings '89 Int'l. Conf. on Parallel Processing, Penn State Univ. Press (Conf. Aug. 8-12, 1989) pp. I-125 et seg.
Papamarcos et al., Proc. of 11th Annual Symposium on Computer Architecture (Conf. Jun. 5-7, 1984) pp. 348 et seg (IEEE).
"High Performance/High Availability Interprocessor Communication Method," IBM Technical Disclosure Bulletin, vol. 31, No. 2, Jul. 1988 pp. 41-42.
Schwartz, Telecommunications Network, "Introduction & Overview" pp. 1-20, Layered Architectures in Data Networks " 71-117.
Haridi et al, "The Cache Coherence Protocol of the Data Diffusion Machine" Parallel Architectures Proceedings, vol. I, pp. 1-18 (1989).
Warren et al, "Data Diffusion Machine-A Scalable . . . ", Proceedings of the International Conference on Fifth . . . , 1988, pp. 943-952.
Hagersten, "Some Issues on Cache-Only Memory Architecture," Scalable Shared-Memory Multiprocessors. May 1990, p. 12.
Hagersten et al, "The Data Diffusion Machine and Its Data Coherency Protocols," Proceedings of the IFIP, pp. 127-148 (1990).

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