Process for fabricating transistors using composite nitride stru

Details Process for fabricating transistors using composite nitride stru Process for fabricating transistors using composite nitride stru

1994-06-28

1997-03-11

Quach, T. N.

Fishing, trapping, and vermin destroying

437 41, 437195, 437200, 437241, H01L 21283

Patent

active

056100990

ABSTRACT:
In fabricating a source/drain electrode of an integrated circuit transistor and a contact window for it: (1) establishing a structure with a window over the source/drain region next to a gate electrode and isolation structure; (2) establishing a dielectric layer covering the isolation structure, the window, and gate electrode; (3) implanting a moderate concentration of impurities into the source/drain region through said dielectric layer so that the moderate concentration region extends partially under the gate electrode; (4) removing the horizontal portions of the dielectric layer with an anisotropic etch thereby leaving the dielectric on vertical side walls; (5) establishing a region of titanium silicide over the moderately dosed source/drain region and establishing a titanium nitride layer over the isolation structure, windows, and gate electrode; (6) establishing a layer of silicon nitride over the titanium nitride layer; (7) implanting the substrate with a relatively heavier dose of ions through the silicon nitride, titanium nitride, and titanium silicide layers to create a heavier concentration source/drain region intersecting said moderate concentration region, where the heavy concentration region does not underlie the gate electrode; (8) patterning the silicon nitride layer; (9) using the patterned silicon nitride layer as a mask to pattern the titanium nitride layer; (10) adding thick interlevel dielectric over the patterned nitride layers; (11) opening windows over the electrodes; and (12) adding contact material in said windows.

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