Method of fabricating field effect transistors having lightly do

Details Method of fabricating field effect transistors having lightly do Method of fabricating field effect transistors having lightly do

1995-03-16

1997-03-11

Niebling, John

Fishing, trapping, and vermin destroying

437 44, 437 57, H01L 21265, H01L 218238

Patent

active

056100884

ABSTRACT:
A method of fabricating an FET or CMOS transistor that includes lightly doped drain ("LDD") regions which minimizes oxide loss while requiring a lesser number of masks. Consequently, manufacturing cost, cycle times and yield loss can be minimized. In one aspect, the present invention provides a method of fabricating an FET having a LDD region using only one mask, comprising the sequential steps of (a) providing a substrate having an active region defined by field oxide regions; (b) providing a gate, having side edges, overlying a portion of said active region; (c) forming a barrier material layer over said substrate including said gate; (d) forming an oxide layer over said barrier material layer; (e) selectively etching said oxide layer with respect to said barrier material layer to form oxide sidewall spacers about the side edges of said gate; (f) implanting heavily doped source and drain regions about the side edges of said gate using said oxide sidewall spacers as masks; (g) removing said oxide sidewall spacers; and (h) implanting the lightly doped drain region about one of the side edges of said gate adjacent to said heavily doped drain region.

REFERENCES:
patent: 4764477 (1988-08-01), Chang et al.
patent: 5200351 (1993-04-01), Hadjizadeh-Amini
patent: 5262664 (1993-11-01), Jung-Suk
patent: 5424234 (1995-06-01), Kwon
patent: 5491099 (1996-02-01), Hsu
Wolf, "Silicon Processing for the VLSI Era: vol. 2: Process Integration", pp. 432-441, 1990, Lattice Press, month unknown.

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