Semiconductor memory device storing data and parity bit

Details Semiconductor memory device storing data and parity bit Semiconductor memory device storing data and parity bit

1992-09-24

1994-03-22

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Plural blocks or banks

365200, G11C 800

Patent

active

052971023

ABSTRACT:
A DRAM includes a plurality of first memory arrays and a second memory array. The plurality of first memory arrays are arranged in two lines. The second memory array is provided on one end side of a region including memory arrays. Each of first memory arrays is divided into four blocks, and performs 1/4 divisional operation. The second memory array is divided into four blocks and performs 1/2 divisional operation. Refresh operation of the DRAM can be switched to 1024 refresh cycle and 512 refresh cycle. Each of the first memory arrays includes 1024 word lines, and the second memory array includes 512 word lines corresponding to the 512 refresh cycle.

REFERENCES:
patent: 4947373 (1990-08-01), Yamaguchi
patent: 4961164 (1990-10-01), Miyaoka
patent: 5040152 (1991-08-01), Voss

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