Method of planarization of topologies in integrated circuit stru

Details Method of planarization of topologies in integrated circuit stru Method of planarization of topologies in integrated circuit stru

1989-07-03

1990-09-04

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437238, 437235, 148DIG51, H01L 21465

Patent

active

049544594

ABSTRACT:
A method is disclosed for making a highly planarized integrated circuit structure having deposited oxide portions planarized to the level of adjacent portions of the integrated circuit structure which comprises: depositing, over an integrated circuit structure having first portions at a height higher than the remainder of the integrated circuit structure, a conformal oxide layer having a thickness which exceeds the height of said first portions above the remainder of the integrated circuit structure; forming a patterned mask layer over said deposited oxide layer with one or more openings therein in registry with the higher height first portions of the integrated circuit structure; etching exposed portions of said conformal oxide layer through the mask openings down to a level approximately equal to the level of the unexposed portion of the conformal oxide layer; removing the mask layer; and polishing the oxide layer to remove raised portions of the conformal oxide layer remaining after the etching step to form a highly planarized structure. Optionally, the oxide layer may be further etched anisotropically until the upper surfaces of the underlying integrated circuit structure is exposed.

REFERENCES:
patent: 4662064 (1987-05-01), Hsu
patent: 4789648 (1988-12-01), Chow
Chen, J. Y. et al, "A Fully Recessed Field Isolation technology Using Photo-CVD Oxide", IEDM, vol. 82, 1982, pp. 233-236.
Shibata, T. et al, "A Simplified Box (Buried-Oxide) Isolation technology for Megabit Dynamic Memories", IEDM, vol. 83, 1983, pp. 27-30.

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