Single mask totally self-aligned power MOSFET cell fabrication p

Details Single mask totally self-aligned power MOSFET cell fabrication p Single mask totally self-aligned power MOSFET cell fabrication p

1988-10-12

1990-02-06

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 6, 437 40, 437 41, 437197, 437202, H01L 2140

Patent

active

048988359

ABSTRACT:
A process of forming a power MOSFET that needs only a single masking step. A layer of gate oxide and a layer of polysilicon are formed in turn over one surface of a silicon wafer and the polysilicon layer is partially oxidized to form a covering polyoxide layer. The polyoxide and polysilicon layers are apertured to define the source regions of the cells of the transistor. Donor and acceptor ions are introduced by way of the openings into the wafer to form localized source regions each enclosed by a separate region of the opposite conductivity type, surface portions of which underlie the polysilicon layer and serve as the channels of individual cells of the transistor. Dielectric tabs are provided along the sidewalls of the openings which are then filled by an overlying conductive layer that serves as the source electrode of the transistor for each of the cells. The polysilicon layer serves as a common gate electrode for each of the cells. Another conductive layer is provided on the back surface of the wafer to serve as a common drain electrode for all the cells of the transistor.

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