Register selection mechanism and organization of an instruction

Details Register selection mechanism and organization of an instruction Register selection mechanism and organization of an instruction

1987-08-04

1989-07-11

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 1300, G11C 800

Patent

active

048477591

ABSTRACT:
A register selection mechanism for an instruction prefetch buffer which allows instructions having different lengths to be accessed on the instruction boundaries. The instruction prefetch buffer comprises a one-port-write, two-port-read array (10). Address generation and control logic (16) is responsive to a read pointer (15) for controlling access to odd and oven addresses in the array. Additional logic may be provided to provide an indication that the instruction prefetch buffer is empty.

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Principles of Digital Computer Design, by Abd-Alla et al., Copyright 1976, pp. 196-203.

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