Method and apparatus for prefetching instructions at an improved

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395587, G06F 938

Patent

active

057991642

ABSTRACT:
An improved prefetch program counter (PC) generation circuitry is provided to the prefetch and dispatch unit (PDU) of a pipelined computer system. The prefetch PC generation circuitry factors into consideration the states of dispatched CTIs in various pipeline stages, when generating a new prefetch PC value for instruction prefetching. The dispatched CTI state dependent prefetch PC generation circuitry includes storage circuitry, fetch control circuitry, and fetch PC generation circuitry. Together, the storage circuitry, the fetch control circuitry, and the fetch PC generation circuitry cooperate to prefetch instructions in a CTI state dependent manner, thereby improving the instruction prefetch rate. In one embodiment, two dynamically switchable instruction fetch queues are provided, with one being used as the sequential instruction fetch queue, and the other being used as the target instruction fetch queue.

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patent: 5524224 (1996-06-01), Denman et al.
patent: 5530825 (1996-06-01), Black et al.
patent: 5606676 (1997-02-01), Grochowski et al.

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