Input signal level detecting circuit

Details Input signal level detecting circuit Input signal level detecting circuit

1984-05-24

1988-11-22

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307279, 307268, 307601, 307602, H03K 3013, H03K 3295, H03K 315, H03K 386

Patent

active

047868244

ABSTRACT:
An input signal level detecting circuit includes a first inverter group circuit having first and second inverters connected in series, and a second inverter group circuit having third and fourth inverters connected in series. The input terminals of the first and third inverters are supplied with a signal having first and second levels to be detected. The output terminals of the second and fourth inverters are connected to set and reset terminals of the flip-flop circuit. When the mean level of the first and second levels is V.sub.TM and the threshold voltages of the first to fourth inverters are V.sub.T1 to V.sub.T4, respectively, the relations V.sub.T1 >V.sub.TM ; V.sub.T2 <V.sub.TM ; V.sub.T3 <V.sub.TM and V.sub.T4 >T.sub.TM are satisfied.

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