Process for fabricating compliant layer board with selectively i

Details Process for fabricating compliant layer board with selectively i Process for fabricating compliant layer board with selectively i

Filed on

1988-03-21

Date issued

1989-07-11

Examiner

Robinson, Ellis P.

Patent Class

Stock material or miscellaneous articles

SubClass

Web or sheet containing structurally defined element or...

SubSubClass

Physical dimension specified

Other Related Categories

428339, 428413, 428414, 428422, 4284735, 428901, 428416, 428209, 174 685, 361398, 156289, 156291, 156310, B32B 900

Type

Patent

Status

active

Patent number

048471461

Description

ABSTRACT:
A modified printed wiring board for reducing the cracking of solder joints used to attach ceramic leadless chip carriers to the surface of the printed wiring board. A relatively thin expansion layer is provided on top of the conventional printed wiring board. This expansion layer is bonded to the printed wiring board except at locations underneath the footprint of the chip carrier and solder joints. This expansion layer reduces the stress on solder joints between the ceramic leadless chip carrier and the printed wiring board due to thermal expansion mismatch, to thereby reduce cracking of the solder joint. Prevention of bonding underneath the chip carrier footprint is provided by a thin layer of polytetrafluoroethylene (PTFE). Methods for applying ther PTFE layer are disclosed.

REFERENCES:
patent: 4458294 (1984-07-01), Wamack
patent: 4647508 (1987-03-01), Gazit et al.
patent: 4658332 (1987-04-01), Baker et al.
patent: 4680220 (1987-07-01), Johnson

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