Method of making field effect transistor

Fishing – trapping – and vermin destroying

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437176, 437184, 437912, H01L 21338

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active

052963985

ABSTRACT:
A field effect transistor having an asymmetric gate includes high dopant concentration source and drain regions. The drain region is shallower and of lower dopant concentration than the source region. The drain is spaced from the gate electrode. Therefore, an ideal FET having a reduced short channel effect and having a lower source resistance and high current drivability (gm) is obtained. When the drain region is produced by ion implantation through a film and the source region is produced by the implantation directly into the substrate, only the drain region is separated from the gate. When the insulating film on the source region is separated from the insulating film on the drain region, the insulating film on the source region is reliably selectively removed, whereby high controllability is obtained.

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patent: 4992387 (1991-02-01), Tamura
patent: 5001077 (1991-03-01), Sakai
patent: 5036017 (1991-06-01), Noda
Kimura et al, "Asymmetric Inplantation Self-Alignment Technique for GaAs MESFETs", Japanese Journal of Applied Physics, vol. 27, No. 7, Jul. 1988, pp. L1340-L1343.
Geissberger et al, "A New Refractory Self7-Align Gate Technology for GaAs Microwave Power FET's and MMIC's", IEEE Transactions on Electron Devices, vol. 35, No. 5, 1988, pp. 615-622.
Enoki et al, "Optimization Of GaAs SAINT Structure for Non-Implanted MMIC" NTT Electrical Communications Laboratories, ED86-0 pp. 23-28, date unknown.
Chakravarti et al, "Double-Diffused Metal-Oxide Silicon FET", IBM Technical Disclosure Bulletin, vol. 19, No. 4, 1976, pp. 1162-1163, month unknown.

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