Patent
1996-08-01
1999-03-02
Lee, Thomas C.
G06F 1326
Patent
active
058782796
ABSTRACT:
This invention relates to an integrated HDLC circuit of the type including at least one HDLC controller and one DMA controller, and means for organizing the access to a first external bus for connection to an external memory, via an internal bus to which are connected different entities, which require to have access to the external memory, the internal bus being connected to the first external bus via a memory controller integrated in the HDLC circuit.
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French Search Report from French Patent Application No. 95 09636, filed Aug. 3, 1995.
IBM Technical Disclosure Bulletin, vol. 34, No. 10a, Mar. 1992, New York, US, pp. 259-263, "Transmit Data Control Block Structure Defined To Optimize Performance Of A High Level Data Link Controller Running In A Layered Microcode Environment".
Patent Abstracts of Japan, vol. 13, No. 125 (P-847), Mar. 28, 1989 & JP-A-63 293658 (Hitachi Ltd.).
IBM Technical Disclosure Bulletin, vol. 28, No. 6, Nov. 1985, New York, US, pp. 2633-2634, "Method Of Communication Of a High Speed Communication Adapter".
Lee Thomas C.
SGS-Thomson Microelectronics S.A.
Yuan Chien
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