Method of making a memory cell array structure

Details Method of making a memory cell array structure Method of making a memory cell array structure

1990-01-08

1991-07-23

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 38, 437 60, 437203, 437233, 437235, 437919, H01L 2170

Patent

active

050343416

ABSTRACT:
This invention relates to a memory cell array structure which comprises a low electric resistance semiconductor substrate and a number of memory cells. Each memory cell includes a capacitor portion and a switching element portion substantially provided thereon. The switching element portion comprises as one constituent region thereof one of electrodes, i.e., the second electrode of the capacitor portion. The second electrodes of all the memory cells are integrated altogether to constitute an integral common electrode which provides a separate region between the memory cells. With such a construction of the memory cell array structure, the area occupied by one memory cell is decreased and the cell-to-cell variation in the capacitor capacity is also decreased. This invention also relates to a process for producing such a memory cell array structure.

REFERENCES:
patent: 4763180 (1988-08-01), Hwang et al.
patent: 4833516 (1989-05-01), Hwang et al.
Richardson et al., "A Trench Transistor Cross-Point DRAM Cell", IDEM, 1985, pp. 714-717.
IBM Technical Disclosure Bull., "High Density Cross Point Semiconductor Memory Cell", pp. 199-200 (Dec. 1987).

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