Power sequence controller with wakeup logic for enabling a wakeu

Details Power sequence controller with wakeup logic for enabling a wakeu Power sequence controller with wakeup logic for enabling a wakeu

1997-07-17

1999-03-02

An, Meng-Ai T.

39518222, G06F 100

Patent

active

058782648

ABSTRACT:
A power sequence controller contains wakeup logic for responding to each wakeup event signal intercepted by the power sequence controller. The wakeup logic compares the intercepted wakeup event signal with a wakeup filter mask to determine if the wakeup event signal should be processed or ignored. If the wakeup event signal requires processing, the wakeup logic transitions the system's processor to a working state. The wakeup logic also determines if the intercepted wakeup event signal requires software processing. If so, a non-zero value associated with the wakeup event signal is stored in an interrupt source register, which causes the processor to execute an interrupt handler procedure and process the wakeup event signal when it transitions to a working state. The wakeup logic also evaluates the processor sleep state to determine if transitioning the processor from the sleep state to a working state requires execution of a processor wakeup procedure to return the processor to normal operation. In addition, the wakeup logic evaluates the processor sleep state to determine whether transitioning the processor from the sleep state to a working state requires sending a processor reset signal to processor, where the reset signal causes the processor to perform a warm or cold boot procedure, depending on the processor's sleep state.

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"Advanced Configuration and Power Interface Specification"; Intel, Microsoft, Toshiba, Revision 1.0; Dec. 22, 1996; pp. i-262.

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