Direct memory access control device and method in a multiprocess

Details Direct memory access control device and method in a multiprocess Direct memory access control device and method in a multiprocess

1994-12-19

1996-12-10

Swann, Tod R.

395308, 395311, 395287, 395474, 395448, G06F 1340, G06F 1336, G06F 1208

Patent

active

055840108

ABSTRACT:
A direct memory access control device is used in a multiprocessor system having a plurality of digital data processors and an external common memory connected in common to those digital data processors through a first bus. In the case of transferring data in a direct memory access mode between processors, the transfer of data between the processors is effected by the control device through a second data bus provided in common to the plurality of digital data processors separately from the first bus. Thus, data can be transferred directly in a direct memory access mode between the processors without using the external memory and high-speed transfer can be realized. In addition, the control device comprises registers for storing the status bits of each digital data processor, such as direct memory access request and acceptance signals, corresponding to each digital data processor. Request and acceptance of direct memory access and transfer of data are effected by monitoring the contents of those registers.

REFERENCES:
patent: 4481578 (1984-11-01), Hughes et al.
patent: 4484273 (1984-11-01), Stiffler et al.
patent: 4509140 (1985-04-01), Cheung
patent: 4570220 (1986-02-01), Tetrick et al.
patent: 4608631 (1986-08-01), Stiffler et al.
patent: 4789963 (1988-12-01), Takahashi et al.
patent: 4829420 (1989-05-01), Stahle
patent: 4860249 (1989-08-01), Nicely et al.
patent: 4862350 (1989-08-01), Orr et al.
patent: 4866665 (1989-09-01), Haswell-Smith
patent: 4920480 (1990-04-01), Murakami et al.
patent: 4928224 (1990-05-01), Zulian
patent: 5019962 (1991-05-01), Funabashi et al.
C. Erskine et al "Architecture and Applications of a Second-Generation Digital Signal Processor," 1985, IEEE, pp. 228-231.
K. Kaneko et al, "A 50ns DSP with Parallel Processing Architecture," 1987 IEEE International Solid-State Circuits Conference, Digest of Technical Papers (Feb. 26, 1987), pp. 158-159.

Affiliated with

Also associated with

Rating

Direct memory access control device and method in a multiprocess does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Direct memory access control device and method in a multiprocess, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Direct memory access control device and method in a multiprocess will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-431978