System and method of retiring store data from a write buffer

Details System and method of retiring store data from a write buffer System and method of retiring store data from a write buffer

1993-10-18

1996-12-10

Chan, Eddie P.

Boots, shoes, and leggings

395445, 395464, 395449, 364DIG1, 3642615, 3642617, G06F 1208

Patent

active

055840094

ABSTRACT:
A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.

REFERENCES:
patent: 3916388 (1975-10-01), Shimp et al.
patent: 4131940 (1978-12-01), Moyer
patent: 4251864 (1981-02-01), Kindell et al.
patent: 4408275 (1983-10-01), Kubo et al.
patent: 4456955 (1984-06-01), Yanagita et al.
patent: 4580214 (1986-04-01), Kubo et al.
patent: 4594679 (1986-06-01), George et al.
patent: 4674089 (1987-06-01), Poret et al.
patent: 4682284 (1987-07-01), Shrofer
patent: 4814976 (1989-03-01), Hansen et al.
patent: 4851991 (1989-07-01), Rubinfeld et al.
patent: 4959771 (1990-09-01), Ardini, Jr. et al.
patent: 4961162 (1990-10-01), Nguyenphu et al.
patent: 4992938 (1991-02-01), Cocke et al.
patent: 5075840 (1991-12-01), Grohoski et al.
patent: 5125092 (1992-06-01), Prener
patent: 5168561 (1992-12-01), Vo
patent: 5168571 (1992-12-01), Hoover et al.
patent: 5202972 (1993-04-01), Gusefski et al.
patent: 5230068 (1993-07-01), Van Dyke et al.
patent: 5261071 (1993-11-01), Lyon
patent: 5283890 (1994-02-01), Petolino, Jr. et al.
patent: 5285323 (1994-02-01), Hetherington et al.
patent: 5291586 (1994-03-01), Jen et al.
patent: 5367705 (1994-11-01), Sites et al.
patent: 5404480 (1995-04-01), Suzuki
patent: 5410655 (1995-04-01), Grenfield et al.
patent: 5421026 (1995-05-01), Sato et al.
patent: 5423048 (1995-06-01), Jager
Computer Architecture News, "A VLSI superscalar processor architecture for numerical applications", vol. 19, No. 3, May 1991, New York, US, pp. 160-168.
Electronic Design, "Processor, chip set take computing to new heights", vol. 41, No. 7, Apr. 1, 1993, Hasbrouck Heights, New Jersey, US, pp. 92-100.

Affiliated with

Also associated with

Rating

System and method of retiring store data from a write buffer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method of retiring store data from a write buffer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method of retiring store data from a write buffer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-431950