Reorder buffer configured to allocate storage capable of storing

Details Reorder buffer configured to allocate storage capable of storing Reorder buffer configured to allocate storage capable of storing

1996-07-26

1999-03-02

Lall, Parshotam S.

395391, G06F 938

Patent

active

058782443

ABSTRACT:
A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instructions results regarding a predefined maximum number of concurrently dispatchable instructions. A line of storage is allocated whenever one or more instructions are dispatched. The line of storage remains allocated until each instruction within the line is ready to retire, and then the line is deallocated as the one or more instructions are concurrently retired.

REFERENCES:
patent: 4044338 (1977-08-01), Wolf
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4807115 (1989-02-01), Torng
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4928223 (1990-05-01), Dao et al.
patent: 5053631 (1991-10-01), Perlman et al.
patent: 5058048 (1991-10-01), Gupta et al.
patent: 5129067 (1992-07-01), Johnson
patent: 5136697 (1992-08-01), Johnson
patent: 5197132 (1993-03-01), Steely, Jr. et al.
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5345569 (1994-09-01), Tran
patent: 5355457 (1994-10-01), Shebanow et al.
patent: 5524263 (1996-06-01), Griffith et al.
patent: 5535346 (1996-07-01), Thomas, Jr.
patent: 5548776 (1996-08-01), Colwell
patent: 5560032 (1996-09-01), Nguyen et al.
patent: 5574935 (1996-11-01), Vidwans et al.
patent: 5584038 (1996-12-01), Papworth et al.
patent: 5623628 (1997-04-01), Brayton et al.
patent: 5632023 (1997-05-01), White et al.
patent: 5689720 (1997-11-01), Nguyen et al.
XP 000685600 Gaddis, et al, "A 56-Entry Instruction Reorder Buffer," 1996 IEEE International Solid-State Circuits Conference, vol. 39, Feb. 1996, pp. 212-213 and 447.
XP 000531973 Wallace, et al, "Design and Implementation of a 100MHz Reorder Buffer," Department of Electrical and Computer Engineering, University of California, Proceedings of the Midwest Symposium on Circuits and Systems, published Aug. 3, 1994, pp. 42-45.
International Search Report for PCT/US 98/01474 dated Aug. 20, 1998.
Lenell, John, "A 20MHz CMOS Reorder Buffer for a Superscalar Microprocessor," 4.sup.th NASA Symposium on VLSI Design, 1992, pp. 2.3.1--2.3.12.
Intel, "Chapter 2: Microprocessor Architecture Overview," pp. 2-1 through 2-4.
Michael Slater, "AMD's K5 Designed to Outrun Pentium," Microprocessor Report, vol. 8, No. 14, Oct. 24, 1994, 7 pages.
Sebastian Rupley and John Clyman, "P6: The Next Step?," PC Magazine, Sep. 12, 1995, 16 pages.
Tom R. Halfhill, "AMD K6 Takes On Intel P6," BYTE, Jan. 1996, 4 pages.
Gaddis, et al, "FP 13.2: A 56 Entry Instruction Reorder Buffer," ISSCC96/Session 13/Microprocessors/Paper FP. 13.2, 1996 IEEE International Solid-State Circuits Conference, pp. 212-213, 447.
Wallace, et al, "Design and Implementation of a 100 MHz Reorder Buffer," Department of Electrical and Computer Engineering, University of California, Irvine, 0-7803-2428-May 1995, 1995, IEEE, pp. 42-45.

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