Semiconductor package with a controlled impedance bus and...

Details Semiconductor package with a controlled impedance bus and... Semiconductor package with a controlled impedance bus and...

2009-11-30

2011-12-13

Gebremariam, Samuel (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Superconductive contact or lead

On integrated circuit

Reexamination Certificate

active

08076759

ABSTRACT:
An apparatus includes a first substrate having a set of semiconductor devices formed within it. The apparatus also includes a second substrate. A third substrate has a data conductor coupled between first and second connections to the second substrate. The data conductor is coupled to the set of semiconductor devices at respective connection points.

REFERENCES:
patent: 4636982 (1987-01-01), Takemae et al.
patent: 4766538 (1988-08-01), Miyoshi
patent: 4985867 (1991-01-01), Ishii et al.
patent: 5222047 (1993-06-01), Matsuda et al.
patent: 5307469 (1994-04-01), Mann
patent: 5334962 (1994-08-01), Higgins et al.
patent: 5394528 (1995-02-01), Kobayashi et al.
patent: 5530814 (1996-06-01), Wong et al.
patent: 5559970 (1996-09-01), Sharma
patent: 5614855 (1997-03-01), Lee et al.
patent: 5630106 (1997-05-01), Ishibashi
patent: 5652870 (1997-07-01), Yamasaki et al.
patent: 5655113 (1997-08-01), Leung et al.
patent: 5717871 (1998-02-01), Hsieh et al.
patent: 5717901 (1998-02-01), Sung et al.
patent: 5764590 (1998-06-01), Iwamoto et al.
patent: 5787267 (1998-07-01), Leung et al.
patent: 5793998 (1998-08-01), Copeland et al.
patent: 5798998 (1998-08-01), Fukushima et al.
patent: 5801985 (1998-09-01), Roohparvar et al.
patent: 5808947 (1998-09-01), McClure
patent: 5831925 (1998-11-01), Brown et al.
patent: 5852725 (1998-12-01), Yen
patent: 5893927 (1999-04-01), Hovis
patent: 5897193 (1999-04-01), Nishino
patent: 5933387 (1999-08-01), Worley
patent: 5958033 (1999-09-01), Schubert et al.
patent: 5995379 (1999-11-01), Kyougoku et al.
patent: 6034878 (2000-03-01), Osaka et al.
patent: 6038132 (2000-03-01), Tokunaga et al.
patent: 6047347 (2000-04-01), Hansen et al.
patent: 6064585 (2000-05-01), Mori et al.
patent: 6125157 (2000-09-01), Donnelly et al.
patent: 6138185 (2000-10-01), Nelson et al.
patent: 6141273 (2000-10-01), Ku et al.
patent: 6144220 (2000-11-01), Young
patent: 6144576 (2000-11-01), Leddige et al.
patent: 6175124 (2001-01-01), Cole et al.
patent: 6188595 (2001-02-01), Chevallier
patent: 6191998 (2001-02-01), Reddy et al.
patent: 6214645 (2001-04-01), Kim
patent: 6219785 (2001-04-01), Smith
patent: 6240039 (2001-05-01), Lee et al.
patent: RE37409 (2001-10-01), Barth et al.
patent: 6307256 (2001-10-01), Chiang et al.
patent: 6307769 (2001-10-01), Nuxoll et al.
patent: 6311313 (2001-10-01), Camporese et al.
patent: 6404660 (2002-06-01), Gamini et al.
patent: 6496400 (2002-12-01), Chevallier
patent: 6594818 (2003-07-01), Kim et al.
patent: 6889304 (2005-05-01), Perego et al.
patent: 7626248 (2009-12-01), Gamini et al.
patent: 2001/0016369 (2001-08-01), Zandman et al.
patent: 2004/0019756 (2004-01-01), Perego et al.
patent: 2004/0221106 (2004-11-01), Perego et al.
patent: 887737 (1998-12-01), None
patent: WO 91/16680 (1991-10-01), None
Kirihata, T., et al., “A 390-mm2, 16-Bank, 1-Gb DDR SDRAM with Hybrid Bitline Architecture,” IEEE Journal of Solid-State Circuits, vol. 34, No. 11, Nov. 1999, pp. 1580-1588.
John, L.K., “VaWiRAM: A Variable Width Random Access Memory Module,” 1995 IEEE, 9th International Conference on VLSI Design—1996. pp. 219-224.
Satoh, K. et al., “A 209K-Transistor ECL Gate Array with RAM,” IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1275-1281.
Masumoto, R.T., “Configurable On-Chip RAM Incorporated Into High Speed Logic Array,” Proceedings of the IEEE 1985 Custom Integrated Circuits Conference, May 20-23, 1985, pp. 240-243.
Rynearson, J., “VMEbus Daisy Chains,” Reprinted from the VITA Journal. Originally writtten in Mar. 1997, last pg. of article updated Sep. 15, 1999, 2 pgs.
Minutes of Meeting No. 70, JC-42.3 Committee on RAM Memories, Mar. 9, 1994, Orlando, Florida, 72 pages (see, in particular, p. 62).
Microsoft Computer Dictionary, Copyright 1999, Fourth Edition, p. 145.

Affiliated with

Also associated with

Rating

Semiconductor package with a controlled impedance bus and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor package with a controlled impedance bus and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor package with a controlled impedance bus and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4315505