Logic circuit, logic circuit design method, logic circuit...

Details Logic circuit, logic circuit design method, logic circuit... Logic circuit, logic circuit design method, logic circuit...

2007-05-29

2011-11-22

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S108000, C716S111000, C716S115000, C716S134000, C703S019000

Reexamination Certificate

active

08065645

ABSTRACT:
A latch conversion circuit which is to be added to a basic logic circuit to obtain a latch circuit having an extremely small through delay amount is prepared in advance. Moreover, provided is means for obtaining a latch circuit position whereat the shifting of the clock edge, such as skew or jitter, can be absorbed to the maximum extent possible, and for forming a latch circuit by adding the latch conversion circuit to the basic logic circuit located at the obtained point. Accordingly, a latch circuit which is not, to the extent possible, affected by skew or jitter can be designed.

REFERENCES:
patent: 6828838 (2004-12-01), Anshumali et al.
patent: 7103857 (2006-09-01), Nosowicz
patent: 2003/0149943 (2003-08-01), Yoshikawa
patent: 2003/0200517 (2003-10-01), Jones
patent: H5-256044 (1996-10-01), None
patent: 2001-156598 (2001-06-01), None
patent: 2002-202347 (2002-07-01), None
patent: 2004-56238 (2004-02-01), None
Japanese Office Action with translations.
Harris, D., et al. , “SP 25:7: Skew-Tolerant Domino Circuits”, IEEE Int'l Solid-State Circuits Conf., p. 422 (1997).

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