Patent
1996-11-25
1999-03-02
Beausoliel, Jr., Robert W.
G06F 1100
Patent
active
058782087
ABSTRACT:
Performance projections for processor systems and memory subsystems are important for a correct understanding of work loads within the system. An instruction trace is generally utilized to determine distribution of instructions, identification of register dependencies, branch path analyses and timing. One well known technique for reconstructing an instruction trace can be accomplished by monitoring bus traffic to determine address traces, data addresses and data during the trace, if the initial architectural state is known. The difficulty in reconstructing an instruction trace from monitored bus traffic can be decreased substantially if more definitive information regarding the actual instruction sequence can be obtained. An internal performance monitor within the processor system is utilized to detect each occurrence of the execution of a specified number of instructions and each occurrence of the execution of a specified number of some specific type of instruction such as load instructions or store instructions and generate an output in response to each such occurrence. This information, in addition to each detected occurrence of an external interrupt, is then utilized in combination with the monitored bus traffic to reconstruct an instruction trace utilizing a limited number of output pins.
REFERENCES:
patent: 5115502 (1992-05-01), Tallman
patent: 5146460 (1992-09-01), Ackerman et al.
patent: 5206948 (1993-04-01), De Angelis et al.
patent: 5317711 (1994-05-01), Bourekas et al.
patent: 5327361 (1994-07-01), Long et al.
patent: 5388233 (1995-02-01), Hays et al.
patent: 5440722 (1995-08-01), Vanderspek et al.
patent: 5446876 (1995-08-01), Levine et al.
patent: 5463775 (1995-10-01), DeWitt et al.
patent: 5485574 (1996-01-01), Bolosky et al.
patent: 5491793 (1996-02-01), Somasundaram et al.
patent: 5513317 (1996-04-01), Borchardt et al.
patent: 5519848 (1996-05-01), Wloka et al.
patent: 5537541 (1996-07-01), Wibecan
patent: 5557548 (1996-09-01), Gover et al.
patent: 5724505 (1998-05-01), Argade et al.
Levine Frank Eliot
Starke William John
Welbon Edward Hugh
Beausoliel, Jr. Robert W.
Dillon Andrew J.
Elmore Stephen C.
International Business Machines - Corporation
Salys Casimer K.
LandOfFree
Method and system for instruction trace reconstruction utilizing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for instruction trace reconstruction utilizing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for instruction trace reconstruction utilizing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-430778