Logic simulator and logic simulation method

Details Logic simulator and logic simulation method Logic simulator and logic simulation method

2008-10-16

2011-11-29

Phan, Thai (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S002000, C703S017000, C703S022000, C716S030000, C716S030000

Reexamination Certificate

active

08069025

ABSTRACT:
According to one embodiment, a logical circuit to be simulated includes a timing network and a specific logical device. The timing network transmits a logical value change of an input signal in correspondence with an elapse of time or clock number increments. The specific logical device receives a timing network output signal that appears at an exit node of the timing network, and a logical value change or a logical value after change of the clock. When predetermined constraint information represents a constraint that a time period or the demanded number of clock cycles needed for a transition of a signal level change to pass through a signal path in the timing network is equal to or smaller than a predetermined numerical value (or equal to or larger than a predetermined numerical value), it is checked if the signal input to the specific logical device violates the predetermined constraint information.

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Notice of Reasons for Rejection in Application No. 2007-335286, Mailed Dec. 16, 2008 (17 pages).

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