Delay cell and phase locked loop using the same

Details Delay cell and phase locked loop using the same Delay cell and phase locked loop using the same

2011-05-06

2011-12-06

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S274000, C327S280000, C327S287000

Reexamination Certificate

active

08072254

ABSTRACT:
A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.

REFERENCES:
patent: 6043719 (2000-03-01), Lin et al.
patent: 6771105 (2004-08-01), Andrasic et al.
patent: 6943608 (2005-09-01), Kelkar
patent: 7541854 (2009-06-01), Lee

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