Method and apparatus of operating a non-volatile DRAM

Details Method and apparatus of operating a non-volatile DRAM Method and apparatus of operating a non-volatile DRAM

2008-12-12

2011-11-15

Lappas, Jason (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S222000, C365S185210, C365S196000

Reexamination Certificate

active

08059471

ABSTRACT:
A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by negatively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully discharged. The pass-gate transistor is activated and if the pass-gate transistor is programmed it does not turn on and if it is erased, it turns on. Charge is shared on the complementary pair of precharged bit lines connected to the non-volatile DRAM cell and its associated Dummy non-volatile DRAM cell. A sense amplifier detects the difference in the data state stored in the pass-gate transistor. The program and erase of the non-volatile DRAM cell is accomplished by charge injection from the associated bit line of the non-volatile DRAM cell.

REFERENCES:
patent: 5153853 (1992-10-01), Eby et al.
patent: 5181188 (1993-01-01), Yamauchi et al.
patent: 5331188 (1994-07-01), Acovic et al.
patent: 5973344 (1999-10-01), Ma et al.
patent: 6754108 (2004-06-01), Forbes
patent: 6798008 (2004-09-01), Choi
patent: 6924522 (2005-08-01), Ma et al.
patent: 6996007 (2006-02-01), Ahn et al.
patent: 7099181 (2006-08-01), Ahn et al.
patent: 2006/0274580 (2006-12-01), Forbes
patent: 2009/0161467 (2009-06-01), Lin et al.
patent: 0 557 581 (1993-09-01), None
“A New Architecture for the NVRAM—An EEPROM Backed-Up Dynamic RAM”, by Terada et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 1, Feb. 1988, pp. 86-90.
“An Experimental 256Mb Non-Volatile DRAM with Cell Plate Boosted Programming Technique,” by Anh et al., ISSCC 2004 / Session 2 / Non-Volatile Memory / 2.2, 2004 IEEE International Solid-State Circuits Conference, 0-7803-8267-6/04, 10 pages.
“High Density 5 Volt-Only Compatible Non-Volatile RAM Cell,” by Guterman, IEDM 82, CH1832-5/82/0000-0728 ,copyright 1982, pp. 728-730.
“Challenges for the DRAM Cell Scaling to 40nm,” by Mueller et al., 0-7803-9269-8/05, copyright 2005 IEEE, 4 pages.

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