Address decoder and/or access line driver and method for...

Details Address decoder and/or access line driver and method for... Address decoder and/or access line driver and method for...

2010-07-09

2011-12-13

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S230070, C365S230060, C365S226000

Reexamination Certificate

active

08077538

ABSTRACT:
Address decoders and access line drivers are provided. One such row decoder and access line driver receives power supply voltages in a manner that prevents CHC damage and avoids GIDL currents in transistors in the decoder and driver. The row decoder and a latch in the driver are powered by a first supply voltage, and an output stage in the access line driver is powered by a second supply voltage. The first and second supply voltages are maintained at a relatively low level during standby before an address is decoded. Only after an address is decoded to set the latch are the supply voltages increased to levels needed to drive the access line. Further, before resetting the latch, the first and power supply voltages are decreased to their standby levels. By maintaining the first and second voltages relatively low until after the latch is set and reset, GIDL currents may be avoided and CHC damage may be prevented.

REFERENCES:
patent: 5039882 (1991-08-01), Arakawa
patent: 5742546 (1998-04-01), Devin
patent: 6343031 (2002-01-01), Murata
patent: 7466596 (2008-12-01), Ausserlechner et al.
patent: 7768865 (2010-08-01), Bollu

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