Viterbi decoding apparatus and viterbe decoding method

Details Viterbi decoding apparatus and viterbe decoding method Viterbi decoding apparatus and viterbe decoding method

1997-03-24

1999-03-02

Baker, Stephen M.

Excavating

H03M 1312

Patent

active

058780602

ABSTRACT:
Survivor sequences information is supplied to a RAM 61-1 and a RAM 61-2 as an input Din. The RAM 61-1 and the RAM 61-2 perform an interleaving operation and store the survivor sequences information alternately in accordance with a clock CK1 and a clock CK2 differing in phase from the clock CK1 by half a period. The phases of the clock CK1 and the phase of the clock CK2 are delayed by half a period when a write operation is switched to a read operation with data being outputted at a selector 62 in an appropriate order accordingly. Traced-back data is then inputted from terminal A and terminal B to the selector 62 and outputted from a terminal X after one of these items of data has been selected at a prescribed timing.

REFERENCES:
patent: 5430768 (1995-07-01), Minuhin et al.
Rae, J., et al., "Design and Performance of a VLSI 120 Mb/s Trellis-Coded Partial Response Channel", IEEE Transaction on Magnetics, vol. 31, No. 2, Mar. 1995, pp. 1208-1214.

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