Method and apparatus for pipelining an error detection algorithm

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371 4012, 711169, 711105, G06F 1100

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active

058780599

ABSTRACT:
A method of pipelining an error detection algorithm on an n-bit data word stored in a memory whereby the n-bit data word is first divided into segments. Then, each of the segments of the n-bit data word is read out from memory. Upon receiving a first of the segments, a portion of the error detection algorithm is computed using the first segment to produce a first error check result. Then a next one of the segments of the data word is received, upon which a next portion of the error detection algorithm is computed using the next segment and a most recently calculated check result of a computation of a prior portion of the error detection algorithm. This produces a revised error check result. If necessary, the above-described steps are repeated until all of the segments of the data word have been processed, wherein the revised error check result computed for the last segment is an error detection syndrome for the complete data word.

REFERENCES:
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patent: 4951246 (1990-08-01), Fromm et al.
patent: 5490155 (1996-02-01), Abdoo et al.
patent: 5623506 (1997-04-01), Dell et al.
patent: 5754753 (1998-05-01), Smelser

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